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Apple Inc.

Sr. CAD Engineer-Timing For Transistor-Level Flows & Methodologies

Apple Inc. - Santa Clara, CA

Typically requires at least 3 years of hands on experience in timing, STA, CAD/methodology, etc.

Proficiency in STA and methodologies for timing closure, signal integrity analysis, cross-talk, and OCV (AOCV, POCV) effects, etc.

Proficiency in formal/functional/logic-to-circuit equivalence checking (FEC) techniques and implementation a plus.

Experience with transistor-level tools such as NanoTime, PathMill, ESP (Verilog to Spice equivalence checking), LEC, HSPICE.

Familiar with digital custom circuit designs including dynamic circuit techniques and memories as well as SPICE models and netlists.

Programming in Perl, TCL, or similar language.

Good communicator who can accurately describe issues and follow them through to completion.

Education

BS, MS preferred, degree in technical field

Additional Requirements

Work with design teams to understand and debug tool issues and constraints

Create/maintain flows, scripts and methodologies for transistor level analysis

Work closely with design teams and CAD to drive timing, power, signal integrity, and functional verification closure efforts

Deep analysis of timing paths to identify key issues

Create documentation and help with guidelines/specs

Action

2 days 20 hours ago

Apple Inc.

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Sr. CAD Engineer-Timing For Transistor-Level Flows & Methodologies Apple Inc. - Santa Clara, CA, United States

   

Location: Santa Clara, CA

Company Profile:
Apple designs and creates iPod and iTunes, Mac laptop and desktop computers, the OS X operating system, and the revolutionary iPhone and iPad.